1. Field
The present invention relates to programming non-volatile storage.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory;” and in U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory,” both patents are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states: an erased state and a programmed state that correspond to data “1” and data “0.” Such a device is referred to as a binary device.
A multi-state flash memory cell is implemented by identifying multiple, distinct allowed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the memory cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. In NAND flash memory, that word line is also connected to one cell in each of the NAND strings that utilize the same word line. A problem arises when it's desired to program one memory cell (or subset of memory cells) on a word line without programming other memory cells connected to the same word line. Because the program voltage is applied to all memory cells connected to a word line, an unselected cell (a memory cell that is not to be programmed) on the word line may become inadvertently programmed. The unintentional programming of the unselected memory cell on the selected word line is referred to as “program disturb.”
Several techniques can be employed to prevent program disturb. In one method known as “self boosting,” the unselected bit lines are electrically isolated and a pass voltage (e.g. 7-10 volts) is applied to the unselected word lines during programming. The unselected word lines couple to the unselected bit lines, causing a voltage to exist in the channel of the unselected bit lines, which tends to reduce program disturb. Self boosting causes a voltage boost to exist in the channel which tends to lower the voltage across the tunnel oxide and hence reduce program disturb.
Other techniques to avoid program disturb include Local Self Boosting (“LSB”) and Erased Area Self Boosting (“EASB”). Both LSB and EASB attempt to isolate the channel of previously programmed memory cells from the channel of the memory cell being inhibited. With the LSB technique, the bit line for the memory cell being programmed is at ground and the bit line of the string with the memory cell being inhibited is at Vdd. The program voltage is driven on the selected word line. The word lines neighboring the selected word line are at zero volts and the remaining non-selected word lines are at Vpass. EASB is similar to LSB with the exception that only the source side neighbor word line is at zero volts. Revised Erased Area Self Boosting (“REASB”) is a variation on EASB.
With each of the boosting and programming techniques, a signal needs to be driven on the word lines. In general, word lines have a non-negligible resistance and capacitance, thereby, leading to a significant RC time constant. Consequently, overall NAND Flash write speeds are degraded by the amount of time the system must wait for word lines to reach the targeted program voltages. If the system does not slow down the write process to fully accommodate the RC delay of the word lines, then the threshold voltage distribution of the memory cells being programmed at a given programming voltage (“natural Vt distribution”) will experience a widening. Memory cells near the end of the word line that is connected to the driver typically have higher threshold voltages, while memory cells at the other end of the word line will have lower threshold voltages. Wider natural Vt distributions can have a number of detrimental effects, such as slower data programming, worse program disturb, or wider final programmed distributions.